AKD4371-B Datasheet, PDF (3/33 Pages) Asahi Kasei Microsystems – 24bit DAC with Headphone Amplifier

[AKD4371-B]
(1) PLL Master Mode
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR). BICK and LRCK are supplied from
PORT2.It is possible to evaluate at various sampling frequencies using built-in the AK4371’s PLL.
AK4371
MCKI
MCKO
BICK
LRCK
SDATA
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
DSP or μP
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
Figure 2. PLL Master Mode
The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of
DSP. The JP3(LRCK2) and JP4(BICK2)’s right side should be connected to LRCK and BICK of DSP.
In case of supplying MCKO to DSP, the test pin(MCKO) should be connected to MCLK of DSP.
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP5
MCLK
JP6
BICK
JP7
LRCK
JP8
SDTO
<KM086201>
-3-
2007/07