AKD4340-SB Datasheet, PDF (4/31 Pages) Asahi Kasei Microsystems – 192kHz sampling 24Bit ΔΣ DAC

ASAHI KASEI
The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4.
OCKS1
0
1
1
OCKS0
MCLK Frequency
0
256fs @fs=88.2/96kHz
0
512fs @ fs=32/44.1/48kHz
1
128fs @ fs=176.4/192kHz
Table 4. MCLK Clock
Default
„ SW1 setting
[SW1](PDN): Reset of AK4340. Select “H” during operation.
[AKD4340-SB]
<KM079900>
4
2005/12