AK8181D Datasheet, PDF (4/6 Pages) Asahi Kasei Microsystems – AK8181D Evaluation Board

Output load circuit
It can terminate by the following three methods. (Pattern A/B/C)
The state of initial shipment is 【Pattern A】.
Pattern A
Q0,1,2,3 ^Zo=50Ω
※with applying power to the VDD-2V terminal
short
AKD8181D
Q0N,1N, ^Zo=50Ω
2N,3N
short
Pattern B
Q0,1,2,3 ^Zo=50Ω
Q0N,1N, ^Zo=50Ω
2N,3N
※without applying power to the VDD-2V terminal
0Ω
0Ω
0Ω
Pattern C
Q0,1,2,3 ^Zo=50Ω
Q0N,1N, ^Zo=50Ω
2N,3N
※without applying power to the VDD-2V terminal
0Ω
RTT
0.1uF
0Ω
※ 𝑅𝑇𝑇 =
1
((𝑉_{𝑂𝐻}+𝑉_{𝑂𝐿})/(𝑉𝐷𝐷 − 2)) ^{𝑍0}
AKD8181D-E-00
4
2012/12