AK8160BV2 Datasheet, PDF (4/16 Pages) Asahi Kasei Microsystems – Low Power & Low Jitter Clock Generator for PCI Express

5. Pin Configurations and Functions
[AK8160BV2]
15 14 13 12 11
XIN 16
VSS1 17
VDD1 18
REFOUT 19
REFOUT_OE 20
10 PCIE0n
9 PCIE0p
8 PCIE1n
7 PCIE1p
6 VSS4
12345
Pin No. Pin Name
1
SS_SEL
2
VSS3
3
VDD3
4
VREF
5
VDD4
6
VSS4
7
PCIE1p
8
PCIE1n
9
PCIE0p
10
PCIE0n
Figure 2. AK8160BV2 Package: 20-Pin QFN (Top View)
Pin Type
DI
PWR
PWR
AO
PWR
PWR
DO
DO
DO
DO
Description
SS Modulation Control Pin
This pin must be connected to “H” or “L”. (1)
SS_SEL = “L” : Modulation ratio is 0[%] (Off)
SS_SEL = “H” : Modulation ratio is -0.5 [%]
Ground pin 3
Power Supply Pin 3
Reference Voltage Generation Pin
This pin must be connected to 1F capacitor.
This pin goes to Hi-Z when power down.
Power Supply Pin 4
Ground Pin 4
PCI Express Gen2 Clock Output pin 1 (Positive)
This pin outputs 100MHz.
PCI Express Gen2 Clock Output pin 1 (Negative)
This pin outputs 100MHz.
PCI Express Gen2 Clock Output pin 0 (Positive)
This pin outputs 100MHz.
PCI Express Gen2 Clock Output pin 0 (Negative)
This pin outputs 100MHz.
014003471-E-00
-4-
2014/06