AK1548 Datasheet, PDF (38/42 Pages) Asahi Kasei Microsystems – 8GHz Low Noise Integer-N Frequency Synthesizer

[AK1548]
14. Frequency Change Timing Chart (Recommended Flow)
High
VDD1,VDD2
High
PDN
Register Writing
CP
Address2 Address0 Address1
{PD1}=1 Setting Setting
Hi-Z
Output1
Address2
{PD1}=0
Output2
Frequency Change Sequence ({PD1} control)
High
VDD1,VDD2
High
PDN
Register Writing
CP
Address3 Address0 Address1
{PD1}=0 Setting Setting
Hi-Z
Output1
Output2
Frequency Change Sequence (Initialization Register control)
Note)
The data on Address3 is same as Address2, but {PD1} should be set “0”. Writing in Address3
puts CP output to Hi-Z. The rise-up of LE signal at writing in Address1, which is subsequent
frequency setting up sequence, is trigger for CP Output.
MS1364-E-00
38
2012/1