AK1548 Datasheet, PDF (36/42 Pages) Asahi Kasei Microsystems – 8GHz Low Noise Integer-N Frequency Synthesizer

[AK1548]
13. Block Power-Up Timing Chart (Recommended Flow)
VDD1, VDD2
PDN should be risen up after {PD1}=1 write in.
PDN
LDO
0V
Register Writing
10ms
Register value defined
Address2 Address0 Address1
{PD1}=1
Setting Setting
Address2
{PD1}=0
1.9V
{PD1}=0 write in
CP
Hi-Z
Output
Power-Up Sequence (PDN control case)
Note)
After powers on, the initial setting of registers is undefined. It is required to write in Address0,
1 and 2 to settle them. It is recommended that [PDN] pin is risen up after Address2 {PD1}=1
write in. It takes about 10ms from PDN rise-up to LDO rise-up. The power-up by register
({PD1}=0 write in) should be done after LDO rise-up.
MS1364-E-00
36
2012/1