AK4129 Datasheet, PDF (34/50 Pages) Asahi Kasei Microsystems – 6ch 216kHz / 24-Bit Asynchronous SRC

[AK4129]
Case 2
External clocks
(Input port)
SDTI
External clocks
(Output port)
PDN
(No Clock)
(Don’t care)
(Don’t care)
I nt ernal Ci rc uit
(Internal state) Power-down _{Power-up Time}
ILRCK1-4
Input wait
SDTO3
SDTO2
SDTO1
UNLOCK
“0” data
“0” data
“0” data
Input Clocks
Input Data
Output Clocks
Don’t care
Don’t care
Don’t care
21ms(max)
(2)
Normal
o per ation
Power-down
Normal data
Normal data
Normal data
“0” data
“0” data
“0” data
Figure 35. System Reset 2
Note 27. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN
pin= “L”.
Note 28. The UNLOCK pin outputs “H” when the PDN pin= “L”. SRC data is output from SDTO1-3 pins, which
corresponds to the each sampling frequency ratio detected SRC, after a rising edge “↑” of PDN if the internal
regulator is in normal operation.
Note 29. (1) is the total time of “Internal circuit power-up + FSO/FSI ratio detection + Clock detection + Internal circuit
group delay”.
Note 30. (2) is the total time of “FSO/FSI ratio detection + Clock detection + Internal circuit group delay”.
MS1173-E-02
- 34 -
2011/06