AK4129 Datasheet, PDF (33/50 Pages) Asahi Kasei Microsystems – 6ch 216kHz / 24-Bit Asynchronous SRC

[AK4129]
■ Regulator
The AK4129 has an internal regulator which suppresses the voltage to 1.8V from DVDD1-4. The generated 1.8V power is
used as power supply for internal circuit. When over-current is flowed to the regulator output, over-current detection circuit
works. When over-voltage is flowed to the regulator output, over-voltage detection circuit works. The regulator block is
powered-down and the AK4129 becomes reset state when over-current detection circuit or over-voltage detection circuit is
operated. The AK4129 does not return to normal operation without a reset by the PDN pin when these detection circuits are
worked. When over-current or over-voltage is detected, the PDN pin should be brought into “L” at once, and should be set
to “H” again to recover normal operation.
The UNLOCK pin indicate the internal status of the device, and outputs “L” in SRC normal operation, and outputs “H”
when over-current or over-voltage are detected.
■ System Reset
Bringing the PDN pin = “L” sets the AK4129 power-down mode and initializes the digital filters. The AK4129 should be
reset once by bringing the PDN pin = “L” upon power-up. When PDN pin = “L”, the SDTO1-3 output is “L”. It takes 23ms
(max) for SDTO output enable after power-down state is released by a clock input. Until then, the SDTO1-3 outputs “L”.
The internal SRC circuit is powered-up on an edge of ILRCK1-3 after a power-up time period of the internal regulator.
(SDTO is identified as SDTO1, SDTO2 and SDTO3. SDTI is identified as SDTI1, SDTI2 and SDTI3.)
Case 1
External clocks
(Input port) ^{Don’t care}
SDTI
Don’t care
External clocks
(Output port)
Don’t care
Input Clocks 1
Input Data 1
Output Clocks 1
PDN
(Internal state) Power-down
23ms(max)
(1)
Normal
operati on
Input Clocks 2
Input Data 2
Output Clocks 2
Don’t care
Don’t care
Don’t care
23ms(max)
PD
(1)
Normal
operation
P ower-d own
SDTO3
SDTO2
SDTO1
UNLOCK
“0” data
“0” data
“0” data
Normal data
Normal data
Normal data
“0” data Normal data
“0” data
“0” data Normal data
“0” data
“0” data
Normal data “0” data
Figure 34. System Reset 1
MS1173-E-02
- 33 -
2011/06