AK1547 Datasheet, PDF (32/37 Pages) Asahi Kasei Microsystems – 4GHz Low Noise Integer-N Frequency Synthesizer

[AK1547]
13. Power-Up Timing Chart (Recommended Flow)
VDD1, VDD2
PDN
Internal register values are set
Address
Register Write-in
0~2
CP
Hi-z
Output
Note1)
After VDD1 and VDD2 is powered up, the initial setting of registers is undefined.
It is required to write in Address0, 1 and 2.
Fig. 10 Power Up Sequence (Recommended)
VDD1, VDD2
PDN
Internal sequence circuit is initialized Internal register values are set
Register Write-in
Address 2
{PD1}=1
Address 2
Address 0,1
{PD1}=0
Undefined
Hi-z
CP
Output
Note2) When VDD1,VDD2 and PDN are synchronously powered up, internal sequence circuit is not
initialized. So the circuit starts working on undefined status. Therefore, register {PD1} must be
set to “1” before register setting.
Fig. 11 Power Up Sequence (VDD1/VDD2/PDN synchronous power-up)
MS1464-E-00
32
2012/9