AK1547 Datasheet, PDF (14/37 Pages) Asahi Kasei Microsystems – 4GHz Low Noise Integer-N Frequency Synthesizer

[AK1547]
4．Lock Detect
Lock detect output can be selected by {LD[2:0]} in <Address2>. When {LD} is set to “101Bin", the phase detector
outputs an un-manipulated phase detection(comparison) result. (This is called “analog lock detect”.) When {LD} is
set to “001Bin”, the lock detect signal is output according to the on-chip logic. (This is called “digital lock detect”.)
The lock detect can be done as following (Case of R>1):
The [LD] pin is in unlocked state (which outputs “Low”) when a frequency setup is made.
In the digital lock detect, the [LD] pin outputs “High” (which means the locked state) when a phase error smaller
than a cycle of [REFIN] clock (T) is detected for N times consecutively. When a phase error larger than T is
detected for N times consecutively while the [LD] pin outputs “High”, then the [LD] pin outputs “Low” (which means
the unlocked state). The counter value N can be set by {LDP} in <Address0>. The N is different between
“unlocked to locked” and “locked to unlocked”.
Table 6 Lock Detect Precision
{LDP}
unlocked to locked
locked to unlocked
0
N=15
N=3
1
N=31
N=7
The lock detect signal is shown below:
Reference clock
PFD frequency signal
Divided clock of RF input signal
PFD output signal
LD Output
This is ignored
because it cannot
be sampled.
Valid
ignored Valid
ignored
The [LD] pin outputs “High” when
a phase error smaller than T is
detected for N times consecutively.
Case of “R = 1”
Reference clock
PFD frequency signal
Divided clock of RF input signal
PFD output signal
LD Output
This is ignored
because it cannot
be sampled.
Valid
Valid
ignored
ignored
The [LD] pin outputs HIGH when
a phase error smaller than T is
detected for N times consecutively.
MS1464-E-00
Case of “R > 1”
Fig. 7 Digital Lock Detect Operations
14
2012/9