AKD5353 Datasheet, PDF (3/17 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.B FOR AK5353

ASAHI KASEI
[AKD5353]
3) All interface signals (MCLK,SCLK,LRCK) are fed from the external circuit through PORT2
PORT2 (DAC/ROM) is used. JP5,7 and 9 should be open. Selection of JP6 is no care but should not be open.
JP4
JP5
JP6
JP7
JP9
XTL
BNC
512FS
256FS
32FS
64FS
128FS
XTE CLK
MCLK
SCLK
LRCK
n Other jumper pins set up
[JP1](VD): VD of AK5353
3V: independent of VA <default>
VA: same as VA (The connector “3V” should be open.)
[JP2](DGND-AGND): Analog ground and digital ground
open: separated <default>
short: common (The connector “DGND” can be open.)
[JP3](5V-3V): VD of AK5353 and power supply to logic
open: independent <default>
short: same (The connector “3V” should be open.)
[JP8](8402_DIF): Always “MSB”
JP1
VD
3V VA
JP2
DGND AGND
JP3
5V 3V
JP8
8402_DIF
I2S
MSB
n The function of the toggle SW.
Upper-side is “H” and lower-side is “L”.
[SW2]: Resets the CS8402. Keep “H” during normal operation.
[SW4]: Resets the AK5353. Keep “H” during normal operation.
n DIP switch set up.
[SW3]: Sets the mode of AK5353.
No.
Pin
ON
OFF (default)
1
DIF
I2S
MSB justified
2
TTL
TTL interface
CMOS interface
Table 1. DIP switch set-up of AK5353
<KM060503>
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