AKD4537 Datasheet, PDF (3/32 Pages) Asahi Kasei Microsystems – Evaluation board Rev.B for AK4537

ASAHI KASEI
[AKD4537]
(1-3) Evaluation of Loop-back using AK4114
X’tal oscillator (X1) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (ROM).
JP5
BICK2
JP6
LRCK2
JP7
LRCK
JP8
MCLK
JP9
BICK
JP10
SDTI
DIR ADC
(1-4) All interface signals including master clock are fed externally.
PORT3 (ROM) is used. Nothing should be connected to PORT1 (DIR).
JP5
BICK2
JP6
LRCK2
JP7
LRCK
JP8
MCLK
JP9
BICK
JP10
SDTI
DIR ADC
(2) Master mode
(2-1) Evaluation of Recording block (MIC, ADC) using MCLK of AK4114
(2-2) Master clock is fed externally
(2-1) Evaluation of Recording block (MIC, ADC) using MCLK of AK4114
X’tal oscillator (X1) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (ROM). It can be
evaluated at internal loop-back mode (LOOP bit = “1”). It is possible to evaluate at various sampling frequencies
using built-in AK4537’s PLL.
JP5
BICK2
JP6
LRCK2
JP7
LRCK
JP8
MCLK
JP9
BICK
JP10
SDTI
DIR ADC
(2-2) Master clock is fed externally
PORT3 (ROM) is used and MCLK is fed from PORT3. Nothing should be connected to PORT1 (DIR). It can be
evaluated at internal loop-back mode (LOOP bit = “1”). It is possible to evaluate at various sampling frequencies
using built-in AK4537’s PLL.
JP5
BICK2
JP6
LRCK2
JP7
LRCK
JP8
MCLK
JP9
BICK
JP10
SDTI
DIR ADC
<KM069501>
-3-
2002/11