AKD4380 Datasheet, PDF (3/21 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.A FOR AK4380

ASAHI KASEI
[AKD4380]
3) Using AKM’s evaluation board for ADC
To evaluate AK4380 with analog input, the AKM’s evaluation board for ADC can be used. MCLK, BICK and
LRCK are supplied from clock generator on the AKD4380, and analog signal is A/D converted and send to
AKD4380 through PORT2(ADC/ROM). In case of using external master clock through a BNC connector, select
“BNC” on JP12(MCLK) and short JP13(XTE).
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
JP13
XTE
ADC DIR ADC DIR GND DATA
VD GND
4) Feeding all signals from external
Under the following set-up, all external signals can be fed through POTR2.
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
ADC DIR ADC DIR GND DATA
VD GND
JP13
XTE
n Clock (MCLK,BICK,LRCK) set up
In case of using evaluation mode 1), JP9,10 and 17 should be set up as follows.
They need no care for other evaluation mode.
MCLK
128fs
256fs
512fs
JP5
JP8
BICK
(X_MCLK) (X_LRCK)
256/128
LR_128
32fs
64fs
256/128 LR_256/512
32fs
64fs
128fs
512
LR_256/512
32fs
64fs
128fs
Table 1. Clock set up
JP7
(X_BICK)
64fs/32fs
128fs/64fs
32fs
64fs/32fs
128fs/64fs
32fs
64fs/32fs
128fs/64fs
default
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