AKD4368 Datasheet, PDF (3/39 Pages) Asahi Kasei Microsystems – Evaluation board Rev.1 for AK4368

ASAHI KASEI
[AKD4368-A]
M/S should be set to “H” for SW1. SDTI,LRCK,BICK of PORT3 should be connected to SDTO,LRCK,BICK
for DSP. In case of supplying MCKO from DSP, the test pin(MCKO)on sub board should be connected to
MCLK of DSP.
The system clock can be supplied by two ways below.
1) Supplied MCKI from J17
JP12
PHASE
JP13
BICK
JP16
MCLK
JP17
EXT
JP18
LRCK
JP19
SDTI
THR INV DIR ADC
DIR ADC DIR ADC
2) Supplied MCKI from MCLK(PORT3)
JP12
PHASE
JP13
BICK
JP16
MCLK
THR INV DIR ADC
JP17
EXT
JP18
LRCK
JP19
SDTI
DIR ADC DIR ADC
(2) PLL Slave Mode
PORT3 (ROM) is used. BICK,LRCK,SDATA are supplied from DSP. Nothing should be connected to PORT1
(DIR). MCKO is needed for a synchronous singal of BICK and LRCK. M/S should be set to “L” for SW1.
AK4368
MCKI
MCKO
BICK
LRCK
SDATA
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
DSP or µP
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
Figure 3. PLL Slave Mode
The test pin (MCKO) on sub board should be connected to MCLK of DSP. System clock MCKI can be
supplied from J17 or PORT3. Setup of jumper pins is same as (1)PLL Master Mode.
<KM077800>
-3-
2005/02