AK9813B Datasheet, PDF (3/24 Pages) Asahi Kasei Microsystems – 12ch 8bit D/A Converter with EEPROM

ASAHI KASEI
[AK9813B]
„ Pin Description (1)
No. Pin Name
20 DI
17 DO
19 CLK
18 CS/LD
I/O
Function
I Serial Data Input Pin
SEL=High : 16bit data input format
SEL=Low : 14bit data input format
O (SEL=High: CS I/F)
AK9813B reads out the data with LSB first in the 16bit shift
register to DO pin synchronously with falling edge of CLK.
When the CS pin is high level, the DO pin becomes high
impedance. In STATUS mode, the DO pin outputs Ready/Busy
status.
(SEL=Low: LD I/F)
AK9813B reads out the data with MSB first in the 14bit shift
register to DO pin synchronously with falling edge of CLK.
In WRITE mode, the DO pin outputs Ready/Busy status.
I Shift Clock Input Pin (Schmitt-trigger input)
AK9813B takes in the data from DI pin synchronously with rising
edge of the CLK pin. The data are transferred to the internal
shift register.
I Chip Select Input Pin (Schmitt-trigger input)
The CS/LD is internally pulled up to VCC.
(SEL=High: CS I/F)
After the CS pin changes from high level to low level while the
CLK pin is high level, the AK9813B can input the data to the
internal shift register and takes in the data from the DI pin
synchronously with the rising edge of the CLK pin.
After the CS pin changes from high level to low level while the
CLK pin is low level, the AK9813B becomes the status mode
and reads out the Ready/Busy status to the DO pin.
When the CS pin changes from low level to high level regardless
of Low/High level of the CLK pin, the AK9813B removes from
the status mode to the normal mode. The CS pin usually
should be kept at high level.
(SEL=Low: LD I/F)
When the LD pin receives high pulse, the data of the internal
shift register is transferred to the internal decoder or the register
for D/A. The LD pin usually should be kept at low level.
DAD04E-01
-3-
2002/11