AK4629 Datasheet, PDF (28/46 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

[AK4629]
(2) Reset by MCLK, LRCK or BICK stop
The AK4629 is automatically placed in reset state when MCLK, LRCK or BICK is stopped during normal operation
(RSTN pin = “H”). In this reset state, the analog output becomes VCOM voltage, and SDTO1-2, DZF1-2 pins output “L”,
but register values are not initialized. When MCLK, LRCK or BICK are input again, the AK4629 is powered up. After
exiting reset following power-up, the ADC enters initializing cycle. Therefore, SDTO1-2 output data is not stable in 516x
LRCK cycle. After exiting reset following power-up, the DAC enters initializing cycle. The analog output becomes
VCOM voltage during this initializing cycle. Figure 18 shows the reset sequence by clock stop.
RSTN bit
Clock In
MCLK, BICK, LRCK
CLK Stop
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
DZF1/DZF2
Normal Operation
Power-down
Normal Operation
GD ⁽³⁾
Power-down
(4)
“0”data
“0”data
GD ⁽³⁾
(6)
(7)
516/fs ⁽¹⁾
Init Cycle
512/fs (2)
Init Cycle
Normal Operation
Normal Operation
GD
(5)
GD
(6)
10∼11/fs (10)
External
Mute
(8)
Mute ON
Notes:
(1) The analog section of the ADC is initialized after exiting reset state.
(2) The analog section of the DAC is initialized after exiting reset state.
(3) The Digital output corresponding to a specific analog input, and the analog ouput corresponding to a specific digital
input have group delay (GD).
(4) ADC output is “0” data during reset.
(5) Click noise occurs at the end of initilizing cycle of the ADC. Mute the digital output if click noise influences
systemapplications.
(6) Click noise occurs within 20usec from MCLK, LRCK or BICK stop/start.
(7) DZF1-2 pins output “L” during reset.
(8) Mute the analog output externally if click noise (6) influences system applications.
Figure 18. Reset 2 Sequence Example
MS1277-E-02
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2012/03