AK4629 Datasheet, PDF (27/46 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

[AK4629]
■ Reset Function
(1) Reset by RSTN bit
When RSTN bit = “0”, ADC and DACs are powered-down but the internal registers are not initialized. The analog outputs
go to VCOM voltage, DZF1-2 pins output “H” and the SDTO1-2 pins outputs “L”. As some click noise occurs, the analog
output should be muted externally if the click noise influences system application. Figure 17 shows the power-up
sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
Normal Operation
4~5/fs (9)
1~2/fs (9)
Digital Block Power-down
516/fs ⁽¹⁾
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
GD ⁽²⁾
Normal Operation
GD
(3)
“0”data
“0”data
(2)
GD
(6) (5)
(7)
Don’t care
(6)
4∼5/fs (8)
(4)
GD
Notes:
(1) The analog part of the ADC is initialized after exiting reset state.
(2) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(3) ADC outputs “0” data in power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise
influences system application.
(5) The analog outputs become VCOM voltage.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in reset mode. When exiting reset mode, “1” should
be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) The DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 17. Reset Sequence Example
MS1277-E-02
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2012/03