AK4612EQ Datasheet, PDF (27/68 Pages) Asahi Kasei Microsystems – 6/8-Channel Audio CODEC

[AK4612]
ಈ࡞આ໌
■ γεςϜΫϩοΫ
AK4612͸MCLKͷΫϩοΫιʔεͱͯ͠֎෦Clockೖྗ·ͨ͸X’talೖྗΛબ୒͢Δ͜ͱ͕ՄೳͰ͢(Figure 17, Figure
18)É»
εϨʔϒϞʔυ࣌ʹඞཁͳΫϩοΫ͸ɺMCLK, LRCK, BICK Ͱ͢ɻMCLKͱLRCK͸ಉ͢ظΔඞཁ͸͋Γ·
͕͢Ґ૬Λ߹ΘͤΔඞཁ͸͋Γ·ͤΜɻMCLKप೾਺Λઃఆ͢Δํ๏͸ɺDFS1-0 bitͰઃఆ͢Δํ๏ (Manual
Setting Mode) ͱσόΠε಺෦Ͱࣗಈઃఆ͢Δํ๏ (Auto Setting Mode) ͷ2͕ͭ͋Γ·͢ɻManual Setting Mode
(ACKS bit = “0”: Default)Ͱ͸ɺDFS1-0 bitͰαϯϓϦϯάεϐʔυ͕ઃఆ͞Ε(Table 1)ɺ֤εϐʔυͰͷMCLK
प೾਺͸ࣗಈݕग़͞Εɺ಺෦ΫϩοΫ͸ద੾ͳप೾਺ʹࣗಈઃఆ͞Ε·͢(Table 3, Table 4, Table 5)ɻAuto
Setting Mode (ACKS bit = “1”) Ͱ͸ɺMCLKप೾਺͸ࣗಈݕग़͞Ε(Table 6)ɺ಺෦ΫϩοΫ͸ద੾ͳप೾਺ʹࣗ
ಈઃఆ͞ΕΔ(Table 7)ͨΊɺDFS1-0 bitͷઃఆ͸ෆཁͰ͢ɻ
ϚελϞʔυ࣌ʹඞཁͳΫϩοΫ͸MCLKͷΈͰ͢ɻϚελΫϩοΫप೾਺ΛCKS1-0 bit (Table 2)Ͱɺαϯϓ
ϦϯάεϐʔυΛDFS1-0 bit (Table 1)Ͱઃఆ͕ඞཁͰ͢ɻCKS1-0, DFS1-0 bit Λઃఆͨ͠௚Ͱޙ͸BICKͱLRCK
ͷग़ྗप೾਺΍σϡʔςΟʔ͕ཚΕΔ৔߹͕͋Γ·͢ɻిݯON౳ͷϦηοτղআ࣌(PDN pin = “↑”) ͸MCLK
͕ೖྗ͞ΕΔ·Ͱύϫʔμ΢ϯঢ়ଶʹͳΓ·͢ɻ
εϨʔϒϞʔυಈ࡞࣌(PDN pin = “H”)ݯి͍͓ͯʹON౳ͷϦηοτղআ࣌(PDN pin = “↑”)͸MCLK, LRCK͕
ೖྗ͞ΕΔ·Ͱύϫʔμ΢ϯঢ়ଶͰ͢ɻ
௨ৗಈ࡞࣌ʹΫϩοΫͷ͕څڙఀࢭͯ͠࠶౓ΫϩοΫ͕͞څڙΕͨ৔߹ɺग़ྗʹҟԻ͕ൃੜ͢ΔՄೳੑ͕͋
Γ·͢ͷͰɺҟԻ͕໰୊ʹͳΔ৔߹͸֎෦Ͱϛϡʔτ͍ͯͩ͘͠͞ɻ
DFS1
0
0
1
1
DFS0
0
1
0
1
Sampling Speed Mode (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
128kHz~192kHz
N/A
-
(default)
(N/A: Not available)
Table 1.αϯϓϦϯάεϐʔυ (Manual Setting Mode)
CKS1
0
0
1
1
CKS0
0
1
0
1
Normal Speed
Mode
256fs
384fs
512fs
512fs
Double Speed
Mode
256fs
256fs
256fs
256fs
Quad Speed
Mode
128fs
128fs
128fs
128fs
Table 2. ϚελΫϩοΫೖྗप೾਺બ୒ (Master Mode)
(default)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
2.0480
2.8224
3.0720
Table 3. γεςϜΫϩοΫྫ (Normal Speed Mode @Manual Setting Mode)
MS1039-J-01
- 27 -
2009/06