AK4612EQ Datasheet, PDF (19/68 Pages) Asahi Kasei Microsystems – 6/8-Channel Audio CODEC

[AK4612]


Parameter
Symbol
min
typ
Control Interface Timing (4-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN Edge to CCLK “↑”
tCSS
50
CCLK “↑” to CSN Edge
tCSH
50
CDTO Delay
tDCD
CSN “↑” to CDTO Hi-Z
tCCZ
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 22)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Capacitive load on bus
Cb
-
Power-down & Reset Timing
PDN Pulse Width
(Note 23)
tPD
150
PDN “↑” to SDTO valid
(Note 24)
tPDV
518


Note 22. σʔλ͸࠷௿300ns(SCLͷཱͪԼ͕Γ࣌ؒ)ͷؒอ࣋͞Εͳ͚Ε͹ͳΓ·ͤΜɻ
Note 23. ݯి౤ೖ࣌͸PDN pin Λ“L” ʹ͢Δ͜ͱͰϦηοτ͕͔͔Γ·͢ɻ
Note 24. PDN pin Λ্ཱ͔ͪ͛ͯΒͷLRCKͷ্ཱ͕ͪΓͷճ਺Ͱ͢ɻ
Note 25. I²C͸Philips Semiconductorsͷొ࿥঎ඪͰ͢ɻ
max Units
ns
ns
ns
ns
ns
ns
ns
ns
50
ns
70
ns
400 kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
1.0
μs
0.3
μs
-
μs
50
ns
400
pF
ns
1/fs
MS1039-J-01
- 19 -
2009/06