AK09912 Datasheet, PDF (27/42 Pages) HuaXinAn Electronics CO.,LTD – 3-axis Electronic Compass

[AK09912]
7.2.3. READ Instruction
When the R/W bit is set to “1”, AK09912 performs read operation.
If a master IC generates an acknowledge instead of a stop condition after AK09912 transfers the data at a specified address,
the data at the next address can be read.
Address can be 00H to 18H, 30H to 32H, and 60H to 62H. When the address is between 00H and 18H, the address is
incremented 00H  01H  02H  03H  10H  11H ...  18H, and the address goes back to 00H after 18H. When the
address is between 30H and 32H, the address goes back to 30H after 32H. When the address is between 60H and 62H, the
address goes back to 60H after 62H.
AK09912 supports one byte read and multiple bytes read.
7.2.3.1. One Byte READ
AK09912 has an address counter inside the LSI chip. In current address read operation, the data at an address specified by
this counter is read.
The internal address counter holds the next address of the most recently accessed address.
For example, if the address most recently accessed (for READ instruction) is address “n”, and a current address read operation is
attempted, the data at address “n+1” is read.
In one byte read operation, AK09912 generates an acknowledge after receiving a slave address for the READ instruction
(R/W bit=“1”). Next, AK09912 transfers the data specified by the internal address counter starting with the next clock pulse,
then increments the internal counter by one. If the master IC generates a stop condition instead of an acknowledge after
AK09912 transmits one byte of data, the read operation stops.
SDA
S
T
A
R/W="1"
R
T
S
Slave
Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
A
A
C
C
C
K
K
K
Figure 7.10 One Byte READ
S
T
O
P
Data(n+x)
P
A
C
K
7.2.3.2. Multiple Byte READ
By multiple byte read operation, data at an arbitrary address can be read.
The multiple byte read operation requires to execute WRITE instruction as dummy before a slave address for the READ
instruction (R/W bit=“1”) is transmitted. In random read operation, a start condition is first generated then a slave address
for the WRITE instruction (R/W bit=“0”) and a read address are transmitted sequentially.
After AK09912 generates an acknowledge in response to this address transmission, a start condition and a slave address for
the READ instruction (R/W bit=“1”) are generated again. AK09912 generates an acknowledge in response to this slave
address transmission. Next, AK09912 transfers the data at the specified address then increments the internal address counter
by one. If the master IC generates a stop condition instead of an acknowledge after data is transferred, the read operation
stops.
SDA
S
T
A
R/W="0"
R
T
S
T
A
R/W="1"
R
T
S
Slave
Address
Register
Address(n)
S
Slave
Address
A
A
C
C
K
K
Data(n)
A
C
K
Data(n+1)
A
A
C
C
K
K
Figure 7.11 Multiple Byte READ
S
T
O
P
Data(n+x)
P
A
C
K
MS1547-E-02
- 27 -
2014/7