AK5572EN Datasheet, PDF (26/68 Pages) Asahi Kasei Microsystems – 2-Channel Differential 32-bit  ADC

■ Timing Diagram
[1] PCM mode
MCLK
LRCK
BICK
MCLK
LRCK
BICK
[AK5572]
1/fCLK
tdCLKH
tdCLKL
1/fs
tLRH
tLRL
tBCK
tBCKH
tBCKL
50%TVDD
dCLK=tdCLKHfs100
or
tdCLKLfs100
50%TVDD
Duty=tLRHfs100
or
tLRLfs100
VIH
VIL
Figure 17. Clock Timing (Slave mode)
1/fCLK
tCLKH
tCLKL
1/fs
tLRH
50%TVDD
dCLK=tCLKHfCLK100
or
tCLKLfCLK100
Duty=tLRHfs100
VOH
50%TVDD
1/fBCK
tBCKH
tBCKL
50%TVDD
dBCK=tBCKHfBCK100
or
tBCKLfBCK100
Figure 18. Clock Timing (Master mode)
015016766-E-00
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2015/12