AK8973 Datasheet, PDF (25/31 Pages) Asahi Kasei Microsystems – 3-axis Electronic Compass

ASAHI KASEI
[AK8973]
9.2. Operation Description
EEPROM read and write operations are controlled by SCL pin, SDA pin, CAD1 pin, CAD0 pin, and
WEN[4:0] bit. The function of "data transfer" is the same as described in 7.1.
9.2.1. READ Instruction
Data can be read from the EEPROM by accessing an EEPROM address in the read mode (write disabled).
AK8973 has two READ instructions of current address read and random read. To terminate READ operation,
set MODE[1:0] of MS1 to "11" to transit to power-down mode.
9.2.1.1. Current Address READ
AK8973 has an address counter inside the LSI chip. In current address read operation, the data at an address
specified by this counter is read.
The internal address counter holds the next address of the most recently accessed address.
If the address most recently accessed (for WRITE or READ instruction) is address "n", and a current address
read operation is attempted, the data at address "n+1" is read.
For example, if read operations are performed in succession, data is read from 62H, 63H through 67H, 68H,
62H, and so on in this order.
In current address read operation, AK8973 generates an acknowledge after receiving a slave address for the
READ instruction (R/W bit="1"). Next, AK8973 transfers the data specified by the internal address counter
starting with the next clock pulse, then increments the internal counter by one. If the master IC generates a stop
condition instead of an acknowledge after AK8973 transmits one byte of data, the read operation stops.
SDA
S
T
A
R/W="1"
R
T
S
Slave
Address
Data(n)
Data(n+1)
Data(n+2)
A
A
A
A
C
C
C
C
K
K
K
K
Fig. 10 CURRENT ADDRESS READ
S
T
O
P
Data(n+x)
P
A
A
C
C
K
K
9.2.1.2. Random READ
By random read operation, data at an arbitrary address can be read.
Random read operation requires to execute WRITE instruction as dummy before a slave address for the READ
instruction (R/W bit="1") is transmitted. In random read operation, a start condition is first generated then a
slave address for the WRITE instruction (R/W bit="0") and a read address are transmitted sequentially.
After AK8973 generates an acknowledge in response to this address transmission, a start condition and a slave
address for the READ instruction (R/W bit="1") are generated again. AK8973 generates an acknowledge in
response to this slave address transmission. Next, AK8973 transfers the data at the specified address then
increments the internal address counter by one. If the master IC generates a stop condition instead of an
acknowledge after data is transferred, the read operation stops.
SDA
S
T
A
R/W="0"
R
T
S
T
A
R/W="1"
R
T
S
Slave
Address
Register
Address(n)
S
Slave
Address
A
A
C
C
K
K
Data(n)
A
C
K
Data(n+1)
A
A
C
C
K
K
Fig. 11 RANDOM READ
S
T
O
P
Data(n+x)
P
A
A
C
C
K
K
MS0561-E-01 <Preliminary>
- 25 -
2007/01