AK5576 Datasheet, PDF (25/69 Pages) Asahi Kasei Microsystems – 6-Channel Differential 32-bit ADC

[AK5576]
(Ta= 40 - +105 C; AVDD= 4.75-5.25 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”),
VDD18= 1.7-1.98 V (LDOE pin=“L”), C_L= 10 pF)
Parameter
Symbol Min. Typ. Max. Unit
Control Interface Timing (3-Wire Serial mode):
(Figure 25) (Figure 26)
CCLK Period
tCCK
200
-
- ns
CCLK Pulse Width Low
tCCKL
80
-
- ns
Pulse Width High
tCCKH
80
-
- ns
CDTI Setup Timing
tCDS
40
-
- ns
CDTI Hold Timing
tCDH
40
-
- ns
CSN “H” Time
tCSW
150
-
- ns
CSN “↓” to CCLK “↑”
tCSS
50
-
- ns
CCLK “↑” to CSN “↑”
tCSH
50
-
- ns
Control Interface Timing (I²C Bus mode): (Figure 27)
SCL CLOCK Frequency
fSCL
-
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
- µs
Start Condition Hold Tune (Prior to First Clock Pulse)
tHD STA 0.6
-
- µs
Clock Low Time
tLow
1.3
-
- µs
Clock High Time
tHIGH
0.6
-
- µs
Setup Time for Repeated Start Condition
tSU STA 0.6
-
- µs
SDA Hold Time from SCL Falling (Note 21)
tHD DAT 0
-
- µs
SDA Setup Time from SCL Rising
tSU DAT 0.1
-
- µs
Rise Time of Both SDA and SCL Lines
tR
-
-
1.0 µs
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3 µs
Setup Time for Stop Condition
tSU STO 0.6
-
- µs
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
-
50 ns
Capacitive Load on Bus
Cb
-
-
400 pF
Power Down & Reset Timing (Figure 28)
PDN Pulse Width
(Note 22)
PDN Reject Pulse Width
(Note 22)
PDN “↑” to SDTO1-4 valid
(Note 23)
tPD
tRPD
tPDV
150
-
-
-
-
583
- ns
30 ns
- 1/fs
Note 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 22. The AK5576 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held
“L” for more than 150 ns for a certain reset. The AK5576 is not reset by the “L” pulse less than
30 ns.
Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
015016912-E-01
- 25 -
2016/01