AK2504A Datasheet, PDF (25/30 Pages) List of Unclassifed Manufacturers – DS3/STS-1/ES Transceiver

ASAHI KASEI
[AK2504A]
RECEIVER SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ )
Parameter
Symbol Min Typ Max Units
RCLK Pulse Width
DS3
Tpwh 10.1 11.177 12.2 ns
(Note 10, 11) ^{Tpwl 10.1 11.177 12.2 ns}
RCLK Pulse Width
STS-1
Tpwh 8.7 9.645 10.6 ns
(Note 12, 11) Tpwl 8.7 9.645 10.6 ns
RCLK Pulse Width
E3
Tpwh 13.1 14.548 16.0 ns
(Note 13, 11) ^{Tpwl 13.1 14.548 16.0 ns}
EXCLK Duty Cycle (EXCLK Min Rise/Fall time : 5ns)
45
-
55
%
Rise Time, RCLK
(Note 11)
tr
-
-
3.5 ns
Fall Time, RCLK
(Note 11)
tf
-
-
3.5 ns
Delay Time: RCLK high to RPDATA/RNDATA (Note 14) Tdcrd 0
-
3.5 ns
TRANSMITTER SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ )
Parameter
Symbol Min Typ Max
TCLK Duty Cycle (TCLK Min Rise/Fall time : 5ns)
30
- 70
Rise Time, TCLK
(Note 11)
tr
-
- 3.5
Fall Time, TCLK
(Note 11)
tf
-
- 3.5
Setup Time, TPDATA/TNDATA to TCLK Falling
Tstdc
4
-
-
Hold Time, TPDATA/TNDATA to TCLK Falling
Thtdc
5
-
-
Note; 10.
11.
12.
13.
14.
Assumes PLL is locked to 44.736 MHz signal.
The sum of the pulse widths must always meet the frequency specifications.
Assumes PLL is locked to 51.84 MHz signal
Assumes PLL is locked to 34.368MHz signal.
Load cap = 15pF.
Units
%
ns
ns
ns
ns
MS0143-E-01
- 25 -
2004/01