AK2504A Datasheet, PDF (16/30 Pages) List of Unclassifed Manufacturers – DS3/STS-1/ES Transceiver

ASAHI KASEI
[AK2504A]
Clock Acquisition
If a valid input signal is assumed to be already present at the analog input, the maximum time between the
application of device power and error-free operation is typically 20 ms.
Table 11 PLL Lock Acquisition Time
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND** = 0V)
Conditions
Power up
Power : Off -> On
Input data : Valid
Input data restore
Power : On
Input data : Loss -> Valid
**) GND=VSSP= VSSV= VSSB=VSST=VSSS=VSSD=0V
min typ Max Units
20
ms
1.0 5.0 ms
Output Jitter
Typical output jitter characteristics is shown in the table of ANALOG SPECIFICATIONS .
Jitter Transfer
Jitter transfer characteristics is shown in the table of ANALOG SPECIFICATIONS.
Jitter Tolerance
Typical jitter tolerance characteristics is shown in the table of ANALOG SPECIFICATIONS.
DS3/STS-1
Compliance with GR-499-CORE, GR-253-CORE, G.752, G.824
E3
Compliance with ITU-T G.823.
MS0143-E-01
- 16 -
2004/01