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AK4122 Datasheet, PDF (24/53 Pages) List of Unclassifed Manufacturers – 24 BIT 96KHZ SRC WITH DIR | |||
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ASAHI KASEI
[AK4122]
 System Reset
Bringing the PDN pin = âLâ sets the AK4122 power-down mode and initializes the digital filter. When PDN pin = âLâ,
the SDTO output is âLâ. The AK4122 should be reset once by bringing PDN pin = âLâ upon power-up. The SDTO is
valid from less than 100ms after the rising of PDN after clocks are supplied, and until then, outputs âLâ. After the rising
of PDN pin, the SDTIO pin is input pin.
External clocks
(input / output port) donât care
(stable)
donât care
PDN
(internal state)
Power-down
< 100msec
PLL locktime & fs detection
normal operation
Power-down
SDTO
â0â data
Figure 13. System Reset
normal data
â0â data
 Sequence of changing clocks
The recommended sequence of changing clocks is shown as Figure 14. The internal reset is executed when the input or
the output clocks are changed. The SDTO is placed â0â during reset. Within 100ms, the SDTO outputs normal data.
When the frequency transition occurs gradually without the phase change, the output data may have large distortion for
several seconds. Then, to output normal data within 100ms, a reset by PDN pin = âLâ or PWN bit = â0â is recommended
when clocks are changed.
External clocks
(input port
state 1 (44.1kHz)
(unknown)
or output port)
state 2 (48kHz)
PDN pin or
PWN bit
< 100msec
(internal state)
normal operation
Power down
PLL locktime
& fs detection
normal operation
SDTIO / SDTO normal data
Note1
normal data
SMUTE (Note2,
recommended)
0dB
Att.Level
-âdB
1024/fso
1024/fso
Figure 14. Sequence of changing clocks
Note 1. The data on SDTO may cause click noise. If SDTI or SDTIO is â0â from GD before PDN pin goes âLâ,
the data on SDTO keeps â0â then no unknown data is output.
Note 2. SMUTE can remove the unknown data.
MS0267-E-02
- 24 -
2004/07
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