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AK4122 Datasheet, PDF (11/53 Pages) List of Unclassifed Manufacturers – 24 BIT 96KHZ SRC WITH DIR | |||
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ASAHI KASEI
Parameter
Symbol
min
typ
Output for PORT3 (Slave mode)
BICK Period
tBCK
1/64fs
BICK Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK Edge to BICK âââ
(Note 11) tLRB
30
BICK âââ to LRCK Edge
(Note 11) tBLR
30
LRCK to SDTO (MSB) (Except I2S mode)
tLRS
BICK âââ to SDTO
tBSD
Output for PORT2 (Master mode)
BICK2 Frequency
fBCK
64fs
BICK2 Duty
BICK2 âââ to LRCK2
BICK2 âââ to SDTIO
dBCK
50
tMBLR
â20
tBSD
â20
Output for PORT3 (Master mode)
BICK Frequency
fBCK
64fs
BICK Duty
BICK âââ to LRCK
BICK âââ to SDTO
dBCK
50
tMBLR
â20
tBSD
â20
Control Interface Timing
CCLK Period
(Note 12) tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN âHâ Time
CSN âââ to CCLK âââ
CCLK âââ to CSN âââ
tCSW
150
tCSS
50
tCSH
50
CDTO Delay
CSN âââ to CDTO Hi-Z
tDCD
tCCZ
Reset Timing
PDN Pulse Width
(Note 13)
tPD
150
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. In case of using INT2. When INT2 is not used, the max value is not limited.
Note 13. The AK4122 can be reset by bringing the PDN pin = âLâ.
[AK4122]
max
30
30
20
30
20
30
1000
45
70
Units
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0267-E-02
- 11 -
2004/07
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