AK4346 Datasheet, PDF (21/31 Pages) Asahi Kasei Microsystems – 3.3V 192kHz 24-Bit 6-Channel DAC

ASAHI KASEI
[AK4346]
(2) I²C-bus Control Mode (I2C pin = “H”)
The AK4346 supports fast-mode I²C-bus system (max: 400kHz).
Figure 15 shows the data transfer sequence at the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 19). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction
bit (R/W) (Figure 16). The most significant five bits of the slave address are fixed as “00100”. The next two bits are
CAD1 and CAD0 (chip address bits). The bits identify the specific device on the bus. The hard-wired input pins (CAD1
and CAD0 pins) set them. If the slave address match that of the AK4346 and R/W bit is “0”, the AK4346 generates the
acknowledge and the write operation is executed. If R/W bit is “1”, the AK4346 generates the not acknowledge since the
AK4346 can be only a slave-receiver. The master must generate the acknowledge-related clock pulse and release the
SDA line (HIGH) during the acknowledge clock pulse (Figure 20).
The second byte consists of the address for control registers of the AK4346. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 17). Those data after the second byte contain control data. The format is MSB
first, 8bits (Figure 18). The AK4346 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 19).
The AK4346 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4346 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead
of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits
address counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed
1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 21) except for the START and the STOP
condition.
SDA
S
T
A
R/W
R
T
S
Slave
Address
Sub
Address(n)
A
A
C
C
K
K
Data(n)
Data(n+1)
A
A
C
C
K
K
S
T
O
P
Data(n+x) P
A
A
C
C
K
K
Figure 15. Data transfer sequence at the I²C-bus mode
0
0
1
0
0 CAD1 CAD0 R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 16. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 17. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 18. Byte structure after the second byte
MS0531-E-00
- 21 -
2006/07