AK5385B Datasheet, PDF (20/24 Pages) Asahi Kasei Microsystems – 24Bit 192kHz ΔΣ ADC

ASAHI KASEI
[AK5385B]
5. Measurement Example
Figure 8 shows the S/(N+D) vs. VREF capacitor that is connected between VREFL/R pins and AVSS pin with the 0.1µF
capacitor in parallel. X-AXIS is the capacity for VREF; Y-AXIS is S/(N+D).
[Measurement Condition]
- AVDD = 5.0V, DVDD = 3.3V; AVSS = BVSS = DVSS = 0V
- fs = 48kHz
- Measurement Bandwidth = 10Hz ∼ 20kHz
- Ta = 25°C
- Using Audio Precision System Two Cascade
S/(N+D) vs. VREF Cap
106.0
105.0
104.0
103.0
102.0
101.0
100.0
0
50
100
150
200
250
VREF Cap [uF]
Lch
Rch
Figure 8. S/(N+D) vs. VREF Cap
6. Synchronization of Multiple Devices
In system where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the MCLK and LRCK must be the same for all of the AK5385Bs in the system. The all
AK5385Bs should be reset at the same timing with preventing the reset signal for AK5385B from overlapping on the edge
of MCLK, so that all AK5385Bs begin sampling on the same clock edge.
MS0406-E-00
- 20 -
2005/08