AK5385B Datasheet, PDF (11/24 Pages) Asahi Kasei Microsystems – 24Bit 192kHz ΔΣ ADC

ASAHI KASEI
[AK5385B]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
2.048
Pulse Width Low
tCLKL
14.5
Pulse Width High
tCLKH
14.5
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
54
Quad Speed Mode
fsq
108
Duty Cycle
Slave mode
45
Master mode
50
Audio Interface Timing
Slave mode
BICK Period
Normal Speed Mode
tBCK
1/128fsn
Double Speed Mode
tBCK
1/64fsd
Quad Speed Mode
tBCK
1/64fsq
BICK Pulse Width Low
tBCKL
33
Pulse Width High
tBCKH
33
LRCK Edge to BICK “↑”
(Note 11) tLRB
20
BICK “↑” to LRCK Edge
(Note 11) tBLR
20
LRCK to SDTO (MSB) (Except I²S mode) tLRS
BICK “↓” to SDTO
tBSD
Master mode
BICK Frequency
fBCK
64fs
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
dBCK
50
tMBLR
−20
tBSD
−20
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
(Note 12) ^tPD
150
(Note 13) ^tPDV
516
max
27.648
54
108
216
55
Units
MHz
ns
ns
kHz
kHz
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
20
ns
20
ns
Hz
%
20
ns
20
ns
ns
1/fs
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK5385B can be reset by bringing the PDN pin = “L”.
Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”. This value is in master mode
This value is longer 1/fs in slave mode than master mode.
MS0406-E-00
- 11 -
2005/08