AKD4368-B Datasheet, PDF (2/32 Pages) Asahi Kasei Microsystems – 24bit DAC with integrated Headphone Amplifier

[AKD4368-B]
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
[VCC] (red) = 5.0V : for SPK-Amp (typ. 5.0V)
[AGND] (black) = 0V : for analog ground
[DGND] (black) = 0V : for logic ground
Each supply line should be distributed from the power supply unit.
3.3V is supplied to AK4368 and AK4116 via the regulator.
2) Set up the evaluation mode, jumper pins. (See the followings.)
3) Power on.
The AK4368 and AK4116 should be resets once bringing SW1(DAC/DIR_PDN) “L” upon power-up.
And the AK7830 should be resets once bringing SW2(SPK_PDN) “L” upon power-up.
Evaluation mode
When evaluating the AK4368 using the PORT1(AK4116), it is possible to use the initial setting of the audio
interface format (24bit MSB justified). When inputting the data from the PORT2, the AK4368’s audio interface
format should be set to correspond the input data’s audio interface format. Refer to the AK4368’s datasheet.
Applicable Evaluation Mode
(1) PLL Master Mode
(2) PLL Slave Mode
(3) EXT Slave Mode
(3-1) In case of using DIR (Optical Link) <default>
(3-2) In case of connecting AK4368 with a external DSP
(1) PLL Master Mode
PORT2(DSP) is used. Nothing should be connected to PORT1(DIR). BICK and LRCK are supplied from
PORT2. It is possible to evaluate at various sampling frequencies using built-in the AK4368’s PLL.
AK4368
MCKI
MCKO
BICK
LRCK
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
DSP or μP
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDATA
SDTO
Figure 2. PLL Master Mode
JP3(MCLK),JP4(BICK),JP5(LRCK) and JP6(SDTO) should be open.
JP8(LRCK2) and JP9(BICK2) should also be open.
The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of
<KM081302>
-2-
2007/08