AK93C45CL Datasheet, PDF (2/16 Pages) Asahi Kasei Microsystems – 1K/2K/4Kbit Serial CMOS EEPROM

ASAHI KASEI
[AK93C45C/55C/65C]
General Description
The AK93C45C/55C/65C is a 1024/2048/4096-bit serial CMOS EEPROM divided into 64/128/256
registers of 16 bits each. The AK93C45C/55C/65C has 6 instructions such as READ, WRITE,
PAGE WRITE, EWEN, EWDS and WRAL. Those instructions control the AK93C45C/55C/65C.
The AK93C45C/55C/65C can operate full function under wide operating voltage range. The
charge up circuit is integrated for high voltage generation that is used for write operation.
A serial interface of AK93C45C/55C/65C, consisting of chip select (CS), serial clock (SK), data-in
(DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard
microprocessors. AK93C45C/55C/65C takes in the write data from data input pin (DI) to a register
synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation,
AK93C45C/55C/65C takes out the read data from a register to data output pin (DO) synchronously
with rising edge of SK.
The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data
output or Busy/Ready signal output.
x Software controlled write protection
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction
is disabled. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must
be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or
VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE,
PAGE WRITE, WRAL, EWEN and EWDS instructions.
x Busy/Ready status signal
After a WRITE, PAGE WRITE, WRAL instruction, the DO output serves as a Busy/Ready status
indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO
indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state.
The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
DAM06E-01
-2-
2005/10