AK4385_06 Datasheet, PDF (2/23 Pages) Asahi Kasei Microsystems – 108dB 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
„ Ordering Guide
AK4385ET
AK4385VT
AKD4385
„ Pin Layout
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
-40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4385
MCLK
1
BICK
2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI
8
Top
View
16
DZFL
15
DZFR
14
VDD
13
VSS
12
AOUTL+
11
AOUTL-
10
AOUTR+
9
AOUTR-
[AK4385]
PIN/FUNCTION
No. Pin Name
I/O Function
1 MCLK
I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK
I Audio Serial Data Clock Pin
3 SDTI
I Audio Serial Data Input Pin
4 LRCK
I L/R Clock Pin
5 PDN
I Power-Down Mode Pin
When at “L”, the AK4385 is in the power-down mode and is held in reset.
The AK4385 must be reset once upon power-up.
6 CSN
I Chip Select Pin
7 CCLK
I Control Data Input Pin
8 CDTI
I Control Data Input Pin in serial mode
9 AOUTR-
O Rch Negative Analog Output Pin
10 AOUTR+
O Rch Positive Analog Output Pin
11 AOUTL-
O Lch Negative Analog Output Pin
12 AOUTL+
O Lch Positive Analog Output Pin
13 VSS
- Ground Pin
14 VDD
- Power Supply Pin
15 DZFR
O Rch Data Zero Input Detect Pin
16 DZFL
O Lch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
MS0246-E-01
-2-
2006/01