AK4954AEN Datasheet, PDF (19/26 Pages) Asahi Kasei Microsystems – 32bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4954A]
Parameter
Symbol min
typ
max
Audio Interface Timing
Master Mode
BICK “↓” to LRCK Edge (Note 35)
LRCK Edge to SDTO (MSB)
(Except I²S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tMBLR
−20
-
20
tLRD
−35
-
35
tBSD
−35
-
35
tSDH
25
-
-
tSDS
20
-
-
Slave Mode
LRCK Edge to BICK “↑” (Note 35)
tLRB
25
BICK “↑” to LRCK Edge (Note 35)
tBLR
25
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
-
BICK “↓” to SDTO
tBSD
-
SDTI Hold Time
tSDH
25
SDTI Setup Time
tSDS
20
Control Interface Timing (I²C Bus Mode): (Note 36)
-
-
-
-
-
45
-
45
-
-
-
-
SCL Clock Frequency
fSCL
-
-
400
Bus Free Time Between Transmissions
tBUF
1.3
-
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
-
Clock Low Time
tLOW
1.3
-
-
Clock High Time
tHIGH
0.6
-
-
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
-
SDA Hold Time from SCL Falling (Note 37)
tHD:DAT
0
-
-
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
-
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
Setup Time for Stop Condition
tSU:STO
0.6
-
-
Capacitive Load on Bus
Cb
-
-
400
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
50
Note 35. この規格値は LRCK のエッジと BICK の “↑”が重ならないように規定しています。
Note 36. I²C-bus は NXP B.V.の商標です。
Note 37.データは最低 300ns (SCL の立ち下がり時間)の間保持されなければなりません。
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
MS1542-J-00-PB
- 19 -
2013/06