AK8456 Datasheet, PDF (18/32 Pages) Asahi Kasei Microsystems – 3 channel input 16bit 30MSPS Video ADC with LED driver

Fig.18 Use Power on Reset
[AK8456]
AVDD
100k
RESETB
0.33F
AK8456
Power on reset circuit is composed by pull-up resistance of RESETB and external capacitor. When
external capacitor is 0.33F, AVDD rise time must be less than 10ms to reset exactly. Staircase-like
supply voltage rising is not allowed.
Fig.19 Power on Reset timing
AVDD (3.3V)
Internal Reference circuits (related to LDO) are activated
immediately. A few mA consumption occurs.
RESETB
LDO start
DVO
(LDO Output) (1.8V)
Access to Register
Not available (Reset)
Available
LEDEN_R/G/
~100ms
LEDEN_R/G/B are must be all low when RESETB rise to high.
When down AVDD to 0V, RESETB level does not became 0V immediately because of charge
remaining in RESETB external capacitor. If up AVDD again before RESETB becoming 0V, power on
reset does not carry out. The time AVDD is 0V must be longer than 300ms for exact power on reset at
re-power up AVDD.
Please control the RESETB from outside without the use of a power-on reset if the above conditions
are not met. During power up AVDD, hold RESETB low level. Then raise RESETB to high level.
014002433-E-00
- 18 -
2014/06