AK7754 Datasheet, PDF (18/26 Pages) Asahi Kasei Microsystems – Audio DSP with Stereo CODEC + MIC/HP-AMP

[AK7754]
■ Reset
(Ta= -20 ºC ~ 85 ºC, AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1=VSS2=VSS3=VSS4=0V)
Parameter
Symbol
min
typ
max
Unit
INITRSTN
(Note 37) tRST
600
ns
Note 37. The INITRSTN pin should be “L” when power up the AK7754.
■ Audio Interface
1) SDIN1/2, SDOUT1/2/M
(Ta= -20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V,
CL=20pF)
Parameter
Symbol
min typ max Unit
DSP Section Input SDIN1/2
Delay Time from BICLK1 “↑” to LRCLK1
tBLRD
20
ns
SCKSEL bit= “0” (Note 38)
Delay Time from LRCLK1 to BITCLK1 “↑”
tLRBD
20
ns
SCKSEL bit= “0” (Note 39)
Delay Time from BICLK2 “↑” to LRCLK2
tBLRD
20
ns
SCKSEL bit= “1” (Note 38)
Delay Time from LRCLK2 to BITCLK2 “↑”
tLRBD
20
ns
SCKSEL bit= “1” (Note 39)
Serial Data Input Latch Setup Time
tBSIDS
80
ns
Serial Data Input Latch Hold Time
tBSIDH
80
ns
SRC Section Input SDIN2 (SCKSEL bit= “1”)
Delay Time from BICLK2 “↑” to LRCLK2 (Note 39)
tBLRD
20
ns
Delay Time from LRCLK2 to BITCLK2 “↑” (Note 39)
tLRBD
20
ns
Serial Data Input Latch Setup Time
Serial Data Input Latch Hold Time
tBSIDS
40
ns
tBSIDH
40
ns
Output SDOUT1, SDOUT2, SDOUTM
Delay Time from LRCLK1 to Serial Data Output (Note 40)
tLRD
80
ns
Delay Time from BICK1 “↓” to Serial Data Output (Note 41)
tBSOD
80
ns
Delay Time from LRCKO to Serial Data Output (Note 40)
tLRD
80
ns
Delay Time from BICKO to Serial Data Output (Note 42)
tBSOD
80
ns
SDIN1/2 →SDOUT1/2
(Note 43)
Delay Time from SDIN1/2 to SDOUT1/2 Output
tIOD
60
ns
Note 38. BITCLKI1 edge must not occur at the same time as LRCLKI1 edge.
Note 39. BITCLKI2 edge must not occur at the same time as LRCLKI2 edge.
Note 40. Except I²S.
Note 41. When BICK1 polarity is reversed, delay time is from BICK1 “↑”.
Note 42. When BICK2 polarity is reversed, delay time is from BICK2 “↑”.
Note 43. SDIN1 → SDOUT1: SELDO1[1:0] bits= “1h”, OUT1E bit= “1”
SDIN2 → SDOUT2: SELDO2[1:0] bits= “1h”, OUT2E bit= “1”
MS1138-E-01-PB
18
2012/03