AK4363 Datasheet, PDF (18/29 Pages) Asahi Kasei Microsystems – 96kHz 24Bit DAC with PLL

ASAHI KASEI
[AK4363]
n Zero detection
When the input data at both channels is continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin
immediately goes to “L” if input data is not zero after going DZF “H”. If RSTN bit becomes “0”, DZF pin goes to “H”.
DZF pin goes to “L” at 4∼5/fs after RSTN bit returns to “1”.
n Soft mute operation
Soft mute operation is performed at digital domain. When the serial control register data of SMUTE goes “1”, the output
signal is attenuated by -∞ during 1024 LRCK cycles. When SMUTE is returned to “0”, the mute is cancelled and the
output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK
cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE bit
0dB
Attenuation
1024/fs
(1)
1024/fs
(3)
-∞
GD
GD
(2)
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input have the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”.
DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 6. Soft mute and zero detection
MS0015-E-01
- 18 -
2000/07