AK4340_10 Datasheet, PDF (17/24 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4340]
■ Mode Control Interface
Some function of the AK4340 can be controlled by pins (parallel control mode) shown in Table 10. The serial control
interface is enabled by the P/S pin = “L”. Internal registers may be written to 3-wire µP interface pins, CSN, CCLK and
CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”,
Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4340 latches the data on the
rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “↑”. The
clock speed of CCLK is 5MHz (max).
Function
Parallel control mode Serial control mode
Double sampling mode at 128/192fs
X
O
De-emphasis
X
O
SMUTE
O
O
16/20/24bit LSB justified format
X
O
Table 10. Function list (O: available, X: not available)
PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4340 should be
reset by PDN pin = “L”. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 13. Control I/F Timing
*The AK4340 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4340 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
■ Register Map
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control 1
ACKS
0
0
DIF2
DIF1
DIF0
PW
RSTN
01H
Control 2
02H
Control 3
03H
Lch ATT
04H
Rch ATT
0
0
ATT7
ATT7
0
0
ATT6
ATT6
0
0
ATT5
ATT5
DFS1
INVL
ATT4
ATT4
DFS0
INVR
ATT3
ATT3
DEM1
0
ATT2
ATT2
DEM0
0
ATT1
ATT1
SMUTE
0
ATT0
ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
MS0501-E-01
- 17 -
2010/09