AK4340_10 Datasheet, PDF (11/24 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4340]
MCLK
1152fs
512fs
768fs
256fs
384fs
128fs
192fs
Sampling Speed
Normal (fs=32kHz Only)
Normal
Double
Quad
Table 3. Sampling Speed (Auto Setting Mode: Default at Serial control mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
-
-
-
-
22.5792
24.5760
192fs
-
-
-
-
-
33.8688
36.8640
MCLK (MHz)
256fs
384fs
512fs
-
-
16.3840
-
-
22.5792
-
-
24.5760
22.5792 33.8688
-
24.5760 36.8640
-
-
-
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
1152fs
36.8640
-
-
-
-
-
-
Sampling
Speed
Normal
Double
Quad
Table 4. System Clock Example (Auto Setting Mode)
■ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. In serial control mode, five serial data mode can be
selected by DIF2-0 bits. (See Table 5). In parallel control mode, two serial data mode can be selected by DIF0 pin. (See
Table 6) In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode
2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I²S Compatible
24bit LSB Justified
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 6
Figure 7
Figure 8
Figure 9
Figure 7
Default
Table 5. Audio Data Format in Serial control mode
Mode
2
3
DIF0
0
1
SDTI Format
24bit MSB Justified
24bit I²S Compatible
BICK
≥48fs
≥48fs
Figure
Figure 8
Figure 9
Table 6. Audio Data Format in Parallel control mode
MS0501-E-01
- 11 -
2010/09