AK4124 Datasheet, PDF (17/24 Pages) Asahi Kasei Microsystems – 192KHZ/ 24BIT HIGH PERFORMANCE ASYNCHRONOUS SRC

ASAHI KASEI
[AK4124]
„ Internal Reset Function for Clock Change
The change of the clock supplied to AK4124 is shown in Figure 13. When the frequency transition occurs gradually
without phase change or the clock of output port is changed keeping fso/fsi > 4, the internal reset is not executed and the
SDTO takes time over 100ms to output normal data. To output normal data within 100ms, please reset by PDN pin = “L”.
External clocks
(Input port
or Output port)
Clocks 1
Don’t care
Clocks 2
PDN pin
< 100ms
(Internal state)
Normal operation Power-down
PLL lock &
fs detection
Normal operation
SDTO
Normal data
Note1
Normal data
SMUTE (Note2,
recommended)
0dB
Att.Level
-∞dB
1024/fso
1024/fso
Figure 13. Sequence of changing clocks
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN pin goes
“L”, which will cause the data on SDTO to remain “0”.
Note 2. SMUTE can also be used to remove the unknown data.
„ UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H”. When PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0288-E-01
- 17 -
2004/08