AK4124 Datasheet, PDF (16/24 Pages) Asahi Kasei Microsystems – 192KHZ/ 24BIT HIGH PERFORMANCE ASYNCHRONOUS SRC

ASAHI KASEI
[AK4124]
„ Dither
The AK4124 has the dither circuit. The dither circuit adds the dither to the LSB of the output data set with the OBIT1-0
pins by DITHER pin = “H" regardless of the SRC mode or the SRC bypass mode.
„ System Reset
Bringing the PDN pin = “L” sets the AK4124 power-down mode and initializes the digital filter. The AK4124 should be
reset once by bringing PDN pin = “L” upon power-up. When PDN pin = “L”, the SDTO output is “L”. The SDTO valid
time is 100ms. Until then, the SDTO outputs “L”.
Case 1
External clocks
(Input port) ^{Don’t care}
SDTI
Don’t care
External clocks
(Output port) ^{Don’t care}
Input Clocks 1
Input Data 1
Output Clocks 1
Input Clocks 2
Input Data 2
Output Clocks 2
Don’t care
Don’t care
Don’t care
PDN
(Internal state) Power-down
< 100ms
PLL lock &
fs detection
Normal
operation
< 100ms
PD
PLL lock &
fs detection
Normal
operation
Power-down
SDTO
“0” data
Normal data
“0” data
Normal data “0” data
UNLOCK
Case 2
External clocks
(Input port)
SDTI
External clocks
(Output port)
PDN
(Internal state) Power-down
Figure 11. System Reset
(No Clock)
(Don’t care)
(Don’t care)
PLL Unlock
Input Clocks
Input Data
Output Clocks
Don’t care
Don’t care
Don’t care
< 100ms
PLL lock &
fs detection
Normal
operation
Power-down
SDTO
“0” data
Normal data “0” data
UNLOCK
Figure 12. System Reset 2
MS0288-E-01
- 16 -
2004/08