AK4420 Datasheet, PDF (16/19 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4420]
1. Grounding and Power Supply Decoupling
VDD, CVDD and VSS are supplied from the analog supply and should be separated from the system digital supply.
Decoupling capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD
and CVDD as possible. The differential voltage between VDD and VSS pins set the analog output range. The power-up
sequence between VDD and CVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically
2.12Vrms (typ @VDD=5V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the
noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1^st-order LPF (Figure 11) can
reduce noise beyond the audio passband. Figure 12 shows example in the case of 10kΩ, 100kΩ terminus.
The output voltage is a positive full scale for 7FFFFFH (@24bit data) and a negative full scale for 800000H (@24bit
data). The ideal output is 0V (VSS) voltage for 000000H (@24bit data). The DC offset is ±60mV or less.
AK4420
AOUT
470
Analog
Out
2.12Vrms (typ)
2.2nF
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 11. External 1^st order LPF Circuit Example1
AK4420
47μ
AOUT
820
220
47k
1000pF
Analog
Out
10kÆ1.92Vrms (typ)
100kÆ2.1Vrms (typ)
Figure 12. External 1^st order LPF Circuit Example2
MS0683-E-02
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2007/12