AK4420 Datasheet, PDF (14/19 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4420]
■ Reset Function
When the MCLK or LRCK stops, the AK4420 is placed in reset mode and its analog outputs are set to VSS (0V, typ).
When the MCLK and LRCK are restarted, the AK4420 returns to normal operation mode. The BICK can be stopped
when MCLK or LRCK is stopped, but it must not be stopped when MCLK and LRCK are supplied.
Internal
State
Normal Operation
Reset
Normal Operation
D/A In
(Digital)
D/A Out
(Analog)
(1)
(3)
VSS
(3)
GD (2)
<Case1:MCLK Stop>
Clock In
MCLK, BICK, LRCK
(4) _{MCLK Stop}
DZF
(6)
<Case2:LRCK Stop>
Clock In
MCLK, BICK, LRCK
(4) (5) _{LRCK Stop}
DZF
(6)
Notes:
(1) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
the “0” data during this period.
(2) The analog output corresponding to a specific digital input has group delay (GD).
(3) No audible click noise occurs under normal conditions.
(4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(5) The AK4420 detects the stop of LRCK if LRCK stops for more than 2048/fs. When LRCK is stopped, the
AK4420 exits reset mode after LRCK is inputted..
(6) The DZF pin is set to “L” in the reset mode.
Figure 9. Reset Timing Example
MS0683-E-02
- 14 -
2007/12