AK2347B Datasheet, PDF (16/34 Pages) Asahi Kasei Microsystems – Two-way Radio Audio & Sub-Audio Processor

ASAHI KASEI
[AK2347B]
14. Digital AC Timing
1) Serial Interface Timing
AK2347B is connected to a CPU by three-wired interface through CSN, SCLK and SDATA pins,
which can make reading and writing data for control registers.
Serial data named SDATA is consist of 1-bit read and write instruction(R/W), 4-bit address (A3 to
A0) and 8-bit data(D7 to D0) in one frame.
Write mode
CSN
SCLK
SDATA
(Input)
SDATA
(Output)
R/W A3 A2 A1 A0
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Read mode
CSN
SCLK
SDATA
(Input)
SDATA
(Output)
R/W A3 A2 A1 A0
Hi-Z
Hi-Z
D7 D6 D5 D4 D3 D2 D1
D0
R/W : Instruction bit controls to write data to AK2347B or read back from it.
When set to low, AK2347B is in write mode. When set to high, AK2347B is in read
mode.
A3 to A0: Register address to be accessed.
D7 to D0: Write or read date to be accessed.
(1) CSN(Chip select) is normally selected high for disable.
When CSN is set to low, serial interface becomes active.
(2) In write mode, instruction, address and data input from SDATA pin are synchronized and
latched with the rising edge of 14 iterations of SCLK clock. Set to low between address A0
and data D7.
In read mode, instruction and address are synchronized and latched with the rising edge of 5
iterations of SCLK clock. And the register data are output from SDATA pin synchronized with
the falling edge of 9 iterations of SCLK clock. The date between address A0 and data D7 is
unstable.
A CPU port to SDATA pin is fixed to High-Z during the interval that SDATA outputs the read
data.
(3) AK2347B assumes that write and read is set by 14 iterations SCLK clock while CSN sets to
Low. If SCLK iterations are less or more than 14 clocks, serial data would not set properly.
MS1419-E-00
- 16 -
2012/05