AK1545 Datasheet, PDF (16/39 Pages) Asahi Kasei Microsystems – 3.5GHz Low Noise Integer-N Frequency Synthesizer

[AK1545]
The lock detect signal is shown below:
Reference clock
PFD frequency signal
Divided clock of RF input signal
PFD output signal (Phase Error)
LD Output
1/2T
Valid
This is ignored
because it cannot
be sampled.
Valid
Case of “R = 1”
ignored
The [LD] pin outputs HIGH when
a phase error smaller than 1/2T is
detected for N times consecutively.
Reference clock
PFD frequency signal
Divided clock of RF input signal
PFD output signal (Phase Error)
LD Output
This is ignored
because it cannot
be sampled.
Valid
T
ignored
Valid
ignored
The [LD] pin outputs HIGH when
a phase error smaller than T is
detected for N times consecutively.
Case of “R > 1”
Fig. 7 Digital Lock Detect Operations
MS1471-E-00
16
2012/10