AK1545 Datasheet, PDF (15/39 Pages) Asahi Kasei Microsystems – 3.5GHz Low Noise Integer-N Frequency Synthesizer

[AK1545]
3．Lock Detect
Lock detect output can be selected by {LD[2:0]} in <Address2>. When {LD} is set to “101Bin", the phase detector
outputs an un-manipulated phase detection(comparison) result. (This is called “analog lock detect”.) When {LD} is
set to “001Bin”, the lock detect signal is output according to the on-chip logic. (This is called “digital lock detect”.)
The lock detect can be done as following:
The [LD] pin is in unlocked state (which outputs “Low”) when a frequency setup (N register or R register settings)
is made.
Case of Lock to Unlock is as following.
R=1: The [LD] pin outputs “High” when a phase error smaller than a half cycle of [REFIN] (1/2T) is detected
for the counter value N times consecutively.
R>1: The [LD] pin outputs “High” when a phase error smaller than a cycle of [REFIN] (T) is detected for the
counter value N times consecutively.
Case of Unlock to Lock is as following.
R=1: The [LD] pin outputs “Low” when a phase error larger than a half cycle of [REFIN] (1/2T) is detected for
the counter value N times consecutively.
R>1: The [LD] pin outputs “Low” when a phase error larger than a cycle of [REFIN] (T) is detected for the counter
value N times consecutively.
The counter value N can be set by {LDP} in <Address0>. The N is different between “unlocked to locked” and
“locked to unlocked”.
{LDP}
0
1
Table 7 Lock Detect Precision
unlocked to locked
locked to unlocked
N=15
N=3
N=31
N=7
MS1471-E-00
15
2012/10