AK1599V Datasheet, PDF (15/41 Pages) Asahi Kasei Microsystems – RF Transmitter for Satellite Communication

[AK1599V]
9.3. Lock Detection
Lock detection output can be selected by LD bit in Address0x04. When LD bit = “1”, LD pin outputs a
phase comparison result which is from phase detector directly (This is called “analog lock detection”).
When LD bit = “0”, the output is the lock detection signal according to the on-chip logic (This is called
“digital lock detection”).
The digital lock detection can be done as following:
LD pin stays unlocked state (which outputs “L”) when frequency setup is made.
In the digital lock detection, LD pin signal rises to “H” (which means the locked state) after a phase error
smaller than a cycle of [REFIN] clock (T) is detected for N times consecutively. After a phase error larger
than T is detected for N times consecutively when LD pin = “H”, LD pin signal drops to “L” (which means
the unlocked state). The counter value N can be set by LDCNTSEL bit in Address0x04. The N is
different between “unlocked to locked” and “locked to unlocked”.
Table11. Lock Detection Precision
LDCNTSEL bit unlocked to locked
“0”
N = 15
“1”
N = 31
locked to unlocked
N=3
N=7
The lock detection signal is shown below:
Reference clock
Phase Comparison signal
T/2
Divided VCO signal
Phase detector signal
This is ignored because it
cannot be sampled.
LD signal
Valid ignore
ignore ^Valid
d
Case of “R = 1” (Note)
ignore
The LD pin outputs HIGH when a
phase error which is smaller than T/2
is detected for N times consecutively.
Reference clock
Phase Comparison signal
T
Divided VCO signal
Phase Detector signal
This is ignored because it
cannot be sampled.
Valid
LD signal
This is ignored
because it cannot
be sampled.
Valid
ignore
The LD pin outputs HIGH when a
phase error which is smaller than T is
detected for N times consecutively.
Case of “R > 1” (Note)
(Note) R is registers in Address0x03
Fig.6 Digital Lock Detection Operations
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