AK8811_12 Datasheet, PDF (13/36 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Encoder

ASAHI KASEI
[AK8811/12]
FUNCTIONAL DESCRIPTION
♦ Reset
When the reset pin [ /RESET ] set to “L”, AK8811/12 is in reset state. AK8811/12 starts in
the internal initializing sequence at the trailing edge of the first SYSCLK after the reset pin is
“L”. All internal registers are set to be default value by this initializing sequence. AK8811/12
needs at least 10 clock counts of SYSCLK for this reset operation. After the reset operation,
the video output pins are in high-impedance. AK8811/12 requires SYSCLK for the reset
operation.
♦ Master-Clock
AK8811/12 requires 27MHz clock at SYSCLK pin for operation. Video input data (ITU-R
BT.656) is sampled at the trailing edge of this 27MHz. SYSINV decides the edge direction.
SYSINV = L Data is sampled at rising edge of SYSCLK.
SYSINV = H Data is sampled at falling edge of SYSCLK.
♦ Video Signal Interface
AK8811/12 can interface with the video input data by the following 3 modes. The mode is
set by the register [ Interface mode register(00H) ].
1. ITU-R BT.656 Format
AK8811/12 decodes EAV in stream data and manages an internal synchronization.
In this case, AK8811/12 outputs FID (odd : “L” even : “H”)/ VSYNC and HSYNC.
CCIR-bit of [ Interface mode register (00H) ] should be set “1” .
2. ITU-R BT.656 like Format (4:2:2 Y/Cb/Cr)
There are Master and Slave modes, for ITU-R BT.656 like Format which does not include
EAV. In this mode, CCIR-bit of [ Interface mode register(00H) ] should be set “0” .
<Master Mode>
AK8811/12 provides FID/VSYNC and HSYNC to an external device according to the
AK8811/12 internal timing counter. AK8811/12 starts to sample the input data at the
fixed value on the internal pixel counter.
In this mode, following setting should be done to [Interface mode register(00H)].
CCIR-bit = 0
MAS-bit = 1
<Slave Mode>
FID/VSYNC and HSYNC are supplied by an external device. AK8811/12 samples the
data as same manner of Master mode.
In this mode, following setting should be done to [Interface mode register(00H)].
CCIR-bit = 0
MAS-bit = 0
Rev.1.1
13
2000/01