|
AK7736AVQ Datasheet, PDF (13/21 Pages) Asahi Kasei Microsystems – 2Ch SRC 内蔵 Audio/HF DSP | |||
|
◁ |
[AK7736A]
â ãã¤ã³ã³ã¤ã³ã¿ãã§ã¼ã¹
(Ta= -40°C ~85°C; VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
min
typ
max Unit
ãã¤ã³ã³ã¤ã³ã¿ãã§ã¼ã¹ç¨ä¿¡å·
SCLK å¨æ³¢æ°
fSCLK
2.1
MHz
SCLK ãã¼ã¬ãã«å¹
tSCLKL
200
ns
SCLK ãã¤ã¬ãã«å¹
tSCLKH
200
ns
ãã¤ã³ã³âAK7736A
CSNãã¤ã¬ãã«å¹
tWRQH
500
ns
CSN âââããPDN âââ
tRST
600
ns
PDN âââããCSN âââ
tIRRQ
1
ms
CSN âââããSCLK âââ
tWSC
500
ns
SCLK âââããCSN âââ
tSCW
800
ns
SI ã©ããã»ããã¢ããæé
tSIS
200
ns
SI ã©ãããã¼ã«ãæé
tSIH
200
ns
AK7736Aâãã¤ã³ã³
SCLKã® âââããSOåºåé
延æé
tSOS
200
ns
SCLKã® âââããSOåºåãã¼ã«ãæé (Note 30) tSOH
200
ns
Note 30. ã³ãã³ãã³ã¼ãã® 8bit ç®å
¥åæã¯é¤ãã¾ãã
â I2CBUSã¤ã³ã¿ãã§ã¼ã¹
(Ta= -40°C ~85°C; VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
min
I2C Timing
SCL clock frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed By Input Filter
tSP
0
Capacitive load on bus
Cb
typ max Unit
400 kHz
μs
μs
μs
μs
μs
0.9
μs
μs
0.3
μs
0.3
μs
μs
50
ns
400
pF
MS1484-J-00-PB
- 13 -
2012/12
|
▷ |