AK4524_12 Datasheet, PDF (12/32 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC

[AK4524]
„ System Clock Input
OPERATION OVERVIEW
The master clock (MCLK) can be either a crystal resonator placed across the XTI and XTO pin, or external clock input to
the XTI pin with the XTO pin left floating. The master clock frequency can be selected by CMODE and CKS0-1 (Table
1). The sampling speed (normal speed mode, double speed mode or four times speed monitor mode) is selected by
DFS0-1 (Table 2). The ADC is powered down during four times speed monitor mode. The frequency of the master clock
output (CLKO) is the same as MCLK frequency and the output can be enabled or disabled by XTALE pin. When the
CLKO output is not used externally, it should be disabled.
When using a crystal oscillator, external loading capacitors (between XTI/XTO and DGND) are required.
In slave mode, the LRCK clock input must be synchronized with MCLK, however the phase is not critical. Internal timing
is synchronized to LRCK upon power-up. All external clocks must be present unless PD =“L” or all parts are powered
down by control register, otherwise excessive current may result from abnormal operation of internal dynamic logic. In
master mode, the clocks should be supplied by critical oscillation except for power down or the external clock (MCLK)
should not be stopped.
DFS1
0
0
1
1
DFS0
0
1
0
1
Sampling Rate
Monitor mode
Normal speed
-
Double speed
-
4 times speed (SDTO = “L”) Simple decimation
4 times speed (SDTO = “L”)
2 tap filter
Table 1. Sampling Speed
at reset
CMODE CKS1
0
0
0
0
0
1
1
0
1
0
CKS0
0
1
0
0
1
MCLK
Normal speed
(DFS1-0 = “00”)
Double speed
(DFS1-0 = “01”)
4 times speed
(DFS1-0 = “10” or “11”)
256fs
N/A
512fs
256fs
1024fs
512fs
384fs
N/A
768fs
384fs
Table 2. Master Clock Frequency Select
N/A
128fs
256fs
N/A
192fs
at reset
M0050-E-04
- 12 -
2012/01